1 of 11 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? replaces 512k x 8 volatile static ram, eeprom or flash memory ? unlimited write cycles ? low - power cmos ? read and write access times of 100ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? optional industrial temperature range of - 40 c to +85 c, designated ind ? jedec standard 32 - pin dip package ? powercap module (pcm) package C directly surface - mountable module C replaceable snap - on powercap provides lithium backup battery C standardized pinout for all nonvolatile sram products C detac hment feature on pcm allows easy removal using a regular screwdriver pin assignment pin description a0 - a18 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+3.3v) gnd - ground nc - no connect ds1250w 3.3v 4096k nonvolatile sram 19 - 5648; rev 12/10 www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 32 - pin encapsulated package 740- mil extended a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 a18 dq2 gnd 15 16 18 17 dq4 dq3 w e nc a15 a16 nc v cc oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17 a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 gnd v bat 34- pin powercap module (pcm) (uses ds9034pc+ or ds9034pci+ powercap) downloaded from: http:///
ds1250w 2 of 9 description the ds1250w 3.3v 4096k nonvolatile sram is a 4,194,304 - bit, fully static, nonvolatile sram organized as 524,288 words by 8 bits. each nv sram has a self - contained lithium energy source and co ntrol circuitry, which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. dip - package ds1250w devices can be used in place of existing 512k x 8 static rams directly conforming to the popular bytewide 32 - pin dip standard. ds1250w devices in the powercap module package are directly surface mountable and are normally pa ired with a ds9034pc po wercap to form a complete nonvolatile sram module. there is no limit o n the number of write cycles that can be executed and no additional support circuitry is requi red for microprocessor interfacing. read mode the ds1250w executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 19 addres s inputs (a 0 - a 18 ) defines which of the 524,288 by tes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providi ng that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce or oe ) and the limiting parame ter is either t co for ce or t oe for oe rather than address access. write mode the ds1250w executes a write cycle whenever the we and ce signals are active (low) after addr ess inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are ena bled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1250w provides full functional capability for v cc greater than 3.0 volts and write protects by 2.8 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become dont care, and all out puts become high - impedance. as v cc falls below approximately 2.5 volts, a power switching circuit connec ts the lit hium energy source to ram to retain data. during power - up, when v cc rises above approximately 2.5 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 3.0 volts. freshness seal each ds1250w device is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than 3.0 volts, the lithium en ergy source is enabled for battery back - up operation. packages the ds1250w is available in two packages: 32 - pin dip and 34 - pin powercap module (pcm). the 32 - pin dip integrates a lithium battery, an sram memory and a nonvolatil e control function into a single package with a jedec - standard 600 - mil dip pinout. the 34 - pin powercap module integrates sram downloaded from: http:///
ds1250w 3 of 9 memory and nonvolatile control into a module base along with conta cts for connection to the lithium battery in the ds9034pc powercap. the powercap module package design al lows a ds1250w pcm device to be surface mounted without subjecting its lithium backup bat tery to destructive high - temperature reflow soldering. after a ds1250w module base is reflow s oldered, a ds9034pc powercap is snapped on top of the base to form a complete nonvolatile sram module. t he ds9034pc is keyed to prevent improper attachment. ds1250w module bases and ds9034pc powercaps a re ordered separately and shipped in separate containers. see the ds9034pc data sheet for further information. downloaded from: http:///
ds1250w 4 of 9 absolute maxim um ratings voltage on any pin relative to ground - 0.3v to +4.6v operating temperature range commercial: 0c to +70c industrial: - 40c to +85c storage temperature edip - 40c to +85c powercap - 55c to +125c lead temperature (soldering, 10 s) +260c soldering temperature (reflow, powercap) +260c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum r ating conditions for extended periods of time ma y affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power supply voltage v cc 3.0 3.3 3.6 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.4 v dc electrical characteristics (t a : see note 10) (v cc = 3.3v 0.3v) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.2v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby curr ent ce =2.2v i ccs1 50 250 a standby current ce =v cc -0.2v i ccs2 30 150 a operating current i cco1 50 ma write protection voltage v tp 2.8 2.9 3.0 v capacitance (t a = + 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf downloaded from: http:///
ds1250w 5 of 9 a c electrical characteristics (t a : see note 10) (v cc = 3.3v 0.3v) parameter symbol ds1250w-100 units notes min max read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 output hi gh - z from deselection t od 35 ns 5 output hold from address change t oh 5 ns write cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 20 ns 12 13 output high - z f rom we t odw 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 20 ns 12 13 read cycle see note 1 downloaded from: http:///
ds1250w 6 of 9 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 12 downloaded from: http:///
ds1250w 7 of 9 power - down/power - up condition power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew from v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = + 25 c) parameter symbol min typ max units notes expected data retention ti me t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load an d are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high - impedance state during this period. downloaded from: http:///
ds1250w 8 of 9 8. if we is low or the we low transition occur s prior to or simultaneously with the ce low transition, the output buffers remain in a high - impedance state during this period. 9. each ds1250w has a built - in switch that disconnects the lithium source until v cc is first applied by the u ser. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, th is range is 0 c to +70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power - down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured fro m ce going high. 14. ds1250 modules are recognized by underwriters laborator ies (u l ) under file e99151. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cycle = 200ns for operating current in put pulse levels: 0 to 2.7v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolerance pin - package speed grade (ns) ds1250w-100+ 0c to +70c 3.3v 0.3v 32 740 edip 100 ds1250wp-100+ 0c to +70c 3.3v 0.3v 34 powercap* 100 ds1250w-100ind+ - 40c to +85c 3.3v 0.3v 32 740 edip 100 DS1250WP-100IND+ - 40c to +85c 3.3v 0.3v 34 powercap* 100 + denotes a lead (pb) - free/rohs - compliant p ackage . * ds9034pc + or ds9034pci + (powercap) required. must be ordered separately. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs sta tu s. package type package code outline no. land pattern no. 32 edip mdt32+6 21-0245 34 pcap pc2+5 21-0246 downloaded from: http:///
ds1250w 9 of 9 revision history revision date description pages changed 121907 added the p ackage information table ; r emoved the dip module package drawing and dimension table 7, 8 12/10 updated the storage information, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the - 150 min/max information from the ac electrical chara cteristics table; updated the ordering information table (removed - 150 parts and leaded - 100 parts) ; updated the package information table 1, 4, 5, 8 downloaded from: http:///
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